Projects

PROJECTS

High Performance NMOS Transistor

On December 17, 1997, a patent application was filed for a High Performance NMOS Transistor which represents a major advancement in silicon chip design for digital applications.

The newly designed SRAM addresses the needs of silicon manufacturers by providing an alternative to CMOS designs that is much more dense, faster and requires 50% less power than conventional NMOS SRAM technology. The new cell's design eliminates the need for P transistors and delivers the following benefits:

The memory cell requires up to 25% less manufacturing processes than required by CMOS.
Chip size up to 33% smaller than CMOS.
Standby current requirement of 50% less than conventional NMOS of equivalent switching speed.
The write speed and switching noise of the cell are improved dramatically.
By using tunnel diodes, performance is increased without sacrificing chip size.

SRAM and DRAM memories are key and integral components of digital computing devices such as microcomputers, workstations, etc. which depend on an ever increasing amount of memory to improve performance and any improvement in chip size amounts to a considerable reduction in cost.